Analog-to-digital (A/D) converters with pipeline architecture are well suited for low power, high speed applications. The pipeline architecture of an A/D converter generally provides high throughput rates and occupy small die areas, which are both desirable and cost efficient in A/D converters. These advantages result from the concurrent operation of each of the multiple stages in the pipeline A/D converter.
FIG. 1 is a block diagram illustrating a conventional conversion stage of a pipeline or cyclic analog-to-digital (A/D) converter. As illustrated in FIG. 1, the conversion stage 100 includes a sample/hold S/H module 110 to receive an analog input voltage VIN 105, a K-bit A/D subconverter module ADSC 120 coupled to an output of the S/H module 110 to estimate the analog input voltage VIN 105 into a digital signal 125 by extracting a predetermined number K of bits from the VIN 105, and a K-bit digital-to-analog (D/A) converter DAC 130 coupled to the ADSC 120 to receive the K-bit signal 125 from the ADSC 120 and to create an analog estimate VDACi 135 of the input voltage VIN 105. A summing circuit 140 coupled to the S/H module 110 and to the DAC 130 subsequently subtracts the analog estimate VDACi 135 from the analog input voltage VIN 105 and transmits the resulting analog residue voltage 145 to an amplifier module AV 150. The AV 150 amplifies the residue voltage 145 by a 2K factor to obtain an amplified residue voltage VOUT 155 and transmits the voltage VOUT 155 to a subsequent conversion stage (not shown) of the A/D converter. The amplified residue voltage VOUT 155 can be calculated with the formulaVOUT=2KVIN−VDACi 
FIG. 2 is a circuit diagram illustrating a conventional 2.5 bit resolution stage implementation for the multistage A/D converter. As illustrated in FIG. 2, the conventional 2.5 bit resolution stage 200 includes an amplifier module 210, capacitor devices 201 through 204 coupled to the inverter input 211 of the amplifier module 210, and several switches, of which switch 221 is coupled to capacitor device 201, switches 222 and 223 are coupled to capacitor device 202, switches 224 and 225 are coupled to capacitor device 203, and switches 226 and 227 are coupled to capacitor device 204. A switch 228 further couples the capacitor device 201 to the output VOUT 213 of the amplifier module 210, and a switch 229 further couples the inverter input 211 of the amplifier module 210 to the ground. Switches 221, 222, 224, and 226 are also coupled to the input voltage VIN, while switches 223, 225, and 227 are coupled to a reference voltage source (not shown), to receive a negative reference voltage −VREF, a zero voltage reference value, or a positive reference voltage +VREF. In FIG. 2, the amplifier module 210 is single-ended. Alternatively, the amplifier module 210 and the entire resolution stage implementation 200 may be fully differential.
During the sampling time period, the switch 229 is closed and the inverter input 211 of the amplifier module 210 is coupled to the ground. The switches 221, 222, 224, and 226 are also closed and the input voltage signal VIN is thus sampled onto the capacitor devices 201 through 204. During the amplifying/hold time period, the switch 228 is closed and the capacitor device 201 is coupled to the output voltage VOUT 213 of the amplifier module 210. The switches 223, 225, and 227 are also closed and the capacitor devices 202 through 204 are coupled to the positive reference voltage +VREF, to the negative reference voltage −VREF, or to a ground reference voltage value, as described in detail below in connection with FIG. 3.
FIG. 3 is a graph illustrating an ideal transfer function of the conventional 2.5 bit converter stage 200 shown in FIG. 2. As shown in FIG. 3, the thresholds transitions coordinates for the illustrated transfer functions are at:                −⅝ Vref, −⅜ Vref, −⅛ Vref, +⅛ Vref, +⅜ Vref, and +⅝ Vref,or        
                                          V            th                    ⁡                      (            k            )                          =                                                            2                ·                k                            -              7                        8                    ·                      V            ref                                              (        1        )            where k=1, . . . , 6.
The following table shows the capacitor connections in various hold operating regions (for the conventional 2.5-bit/stage operation).
TABLE 1RegionC1C2C3C4Vout (ideal)1Out−Vref−Vref−Vref4 * Vin + 3 * Vref2Out0−Vref−Vref4 * Vin + 2 * Vref3Out00−Vref4 * Vin + Vref4Out0004 * Vin5Out00+Vref4 * Vin − Vref6Out0+Vref+Vref4 * Vin + 2 * Vref7Out+Vref+Vref+Vref4 * Vin + 3 * Vref
The actual transfer function equations can be calculated as:
                              V          out                =                                                                              C                  1                                +                                  C                  2                                +                                  C                  3                                +                                  C                  4                                                            C                1                                      ·                          V              in                                +                                                                      ∑                                      i                    =                                          k                      +                      1                                                        4                                ⁢                                                                  ⁢                                  C                  i                                                            C                1                                      ·                          V              ref                                                          (        2        )            for region k<4;
                              V          out                =                                                            C                1                            +                              C                2                            +                              C                3                            +                              C                4                                                    C              1                                ·                      V            in                                              (        3        )            for region k=4, and
                              V          out                =                                                                              C                  1                                +                                  C                  2                                +                                  C                  3                                +                                  C                  4                                                            C                1                                      ·                          V              in                                -                                                                      ∑                                      i                    =                    4                                                        k                    -                    1                                                  ⁢                                                                  ⁢                                  C                  i                                                            C                1                                      ·                          V              ref                                                          (        4        )            for region k>4.
The slope in FIG. 3 is constant in all regions and can be calculated as (C1+C2+C3+C4)/C1.
Assuming some inherent mismatch between the capacitor devices C1-C4:Ci=(1+αi)·C  (5)where α<<1, and C is an average value of the individual capacitor values Ci.
The transition heights between region k to region k+1 can be computed as follows:
for k<4
                              Δ          ⁢                                          ⁢                      V            out                          =                                            C                              k                +                1                                                    C              1                                ·                      V            ref                                              (        6        )            with the error from the ideal transition height of VREF
                    ɛ        =                                            Δ              ⁢                                                          ⁢                              V                out                                      -                          V              ⁢                                                          ⁢              ref                                =                                                                                                                C                                              k                        +                        1                                                              -                                          C                      1                                                                            C                    1                                                  ·                V                            ⁢                                                          ⁢              ref                        ≈                                                            (                                                            α                                              k                        +                        1                                                              -                                          α                      1                                                        )                                ·                V                            ⁢                                                          ⁢              ref                                                          (        7        )            while for k>=4
                              Δ          ⁢                                          ⁢                      V            out                          =                                            C                              k                -                3                                                    C              1                                ·                      V            ref                                              (        8        )            with the error from the ideal transition height of VREF
                    ɛ        =                                            Δ              ⁢                                                          ⁢                              V                out                                      -                          V              ⁢                                                          ⁢              ref                                =                                                                                                                C                                              k                        -                        3                                                              -                                          C                      1                                                                            C                    1                                                  ·                V                            ⁢                                                          ⁢              ref                        ≈                                                            (                                                            α                                              k                        -                        3                                                              -                                          α                      1                                                        )                                ·                V                            ⁢                                                          ⁢              ref                                                          (        9        )            
Thus, what is needed is an A/D converter structure and method that will reduce the transition height errors computed above in equations (7) and (9) and, thus, the non-linearities in the A/D converter structure by a factor of 2, with minimal added complexity and no speed or other performance loss.